Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1385

CPUID—CPU Identification (Continued)
Operation
CASE (EAX) OF
EAX = 0H:
EAX  Highest input value understood by CPUID;
EBX  Vendor identification string;
EDX  Vendor identification string;
ECX  Vendor identification string;
BREAK;
EAX = 1H:
EAX[3:0]  Stepping ID;
EAX[7:4]  Model;
EAX[11:8]  Family;
EAX[13:12]  Processor Type;
EAX[15:14]  Reserved;
EAX[19:16]  Extended Model;
EAX[27:20]  Extended Family;
EAX[31:28]  Reserved;
EBX[7:0]  Brand Index; (* Always zero for processors based on Itanium architecture *)
EBX[15:8]  CLFLUSH Line Size;
EBX[16:23]  Number of logical processors per physical processor;
EBX[31:24]  Initial APIC ID; (* Reserved for processors based on Itanium architecture *)
ECX  Reserved;
EDX  Feature flags;
BREAK;
EAX = 2H:
EAX  Cache and TLB information;
EBX  Cache and TLB information;
ECX  Cache and TLB information;
EDX  Cache and TLB information;
BREAK;
EAX = 80000000H:
EAX  Highest extended function input value understood by CPUID;
EBX  Reserved;
ECX  Reserved;
EDX  Reserved;
BREAK;
EAX = 80000001H:
EAX  Extended Processor Signature and Feature Bits; (* Currently Reserved *)
EBX  Reserved;
ECX  Reserved;
EDX  Reserved;
BREAK;
EAX = 80000002H:
EAX  Processor Name;
EBX  Processor Name;
ECX  Processor Name;
EDX  Processor Name;
BREAK;
EAX = 80000003H:
EAX  Processor Name;
EBX  Processor Name;
ECX  Processor Name;
EDX  Processor Name;
Volume 4: Base IA-32 Instruction Reference 4:83