Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1807

CVTTPS2PI: Packed Single-FP to Packed INT32 Conversion (truncate)
(Continued)
This instruction behaves identically to original MMX technology instructions, in the
Comments:
presence of x87-FP instructions, including:
• Transition from x87-FP to MMX technology (TOS=0, FP valid bits set to all valid).
• MMX technology instructions write ones (1's) to the exponent part of the
corresponding x87-FP register.
Prioritization for fault and assist behavior for CVTTPS2PI is as follows:
Memory source
1. Invalid opcode (CR0.EM=1)
2. DNA (CR0.TS=1)
3. #MF, pending x87-FP fault signalled
4. After returning from #MF, x87-FP->MMX technology transition
5. #SS or #GP, for limit violation
6. #PF, page fault
7. SSE numeric fault (i.e. invalid, precision)
Register source
1. Invalid opcode (CR0.EM=1)
2. DNA (CR0.TS=1)
3. #MF, pending x87-FP fault signalled
4. After returning from #MF, x87-FP->MMX technology transition
5. SSE numeric fault (i.e. precision)
Volume 4: IA-32 SSE Instruction Reference 4:505