Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 971

fcvt.xf
fcvt.xf — Convert Signed Integer to Floating-point
( ) fcvt.xf
Format: qp
The 64-bit significand of FR
Description:
floating-point representation is placed in FR
If FR is a NaTVal, FR
f
2
This operation is always exact and is unaffected by the rounding mode.
Operation:
if (PR[qp]) {
fp_check_target_register(f
if (tmp_isrcode = fp_reg_disabled(f
disabled_fp_register_fault(tmp_isrcode, 0);
if (fp_is_natval(FR[f
FR[f
} else {
tmp_res = FR[f
if (tmp_res.significand{63}) {
} else
tmp_res.exponent = FP_INTEGER_EXP;
tmp_res = fp_normalize(tmp_res);
FR[f
FR[f
FR[f
}
fp_update_psr(f
}
None
FP Exceptions:
Illegal Operation fault
Interruptions:
3:72
=
f f
1 2
is treated as a signed integer and its register file precision
f
2
is set to NaTVal instead of the computed result.
f
1
1
])) {
2
] = NATVAL;
1
];
2
tmp_res.significand = (~tmp_res.significand) + 1;
tmp_res.sign = 1;
tmp_res.sign = 0;
].significand = tmp_res.significand;
1
].exponent = tmp_res.exponent;
1
].sign = tmp_res.sign;
1
);
1
.
f
1
);
, f , 0, 0))
1 2
Disabled Floating-point Register fault
F11
Volume 3: Instruction Reference