Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1680

STR—Store Task Register
Opcode
0F 00 /1
Description
Stores the segment selector from the task register (TR) in the destination operand. The
destination operand can be a general-purpose register or a memory location. The
segment selector stored with this instruction points to the task state segment (TSS) for
the currently running task.
When the destination operand is a 32-bit register, the 16-bit segment selector is copied
into the lower 16 bits of the register and the upper 16 bits of the register are cleared to
0s. With the destination operand is a memory location, the segment selector is written
to memory as a 16-bit quantity, regardless of operand size.
The STR instruction is useful only in operating-system software. It can only be executed
in protected mode.
Operation
IF Itanium System Environment THEN IA-32_Intercept(INST,STR);
DEST  TR(SegmentSelector);
Flags Affected
None.
Additional Itanium System Environment Exceptions
IA-32_Intercept
Protected Mode Exceptions
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Real Address Mode Exceptions
#UD
Virtual 8086 Mode Exceptions
#UD
4:378
Instruction Description
STR r/m16 Stores segment selector from TR in r/m16
Mandatory Instruction Intercept.
If the destination is a memory operand that is located in a
nonwritable segment or if the effective address is outside the CS,
DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it
contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
The STR instruction is not recognized in real address mode.
The STR instruction is not recognized in virtual 8086 mode.
Volume 4: Base IA-32 Instruction Reference