Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1523

INTn/INTO/INT3—Call to Interrupt Procedure (Continued)
FI;
END;
INTER-PRIVILEGE-LEVEL-INTERRUPT
(* PE=1, interrupt or trap gate, non-conforming code segment, DPLCPL *)
(* Check segment selector and descriptor for stack of new privilege level in current TSS *)
IF current TSS is 32-bit TSS
THEN
ELSE (* TSS is 16-bit *)
FI;
IF segment selector is null THEN #TS(EXT); FI;
IF segment selector index is not within its descriptor table limits
OR segment selector's RPL  DPL of code segment,
FI;
Read segment descriptor for stack segment in GDT or LDT;
IF stack segment DPL  DPL of code segment,
OR stack segment does not indicate writable data segment,
FI;
IF stack segment not present THEN #SS(SS selector+EXT); FI;
IF 32-bit gate
THEN
ELSE (* 16-bit gate *)
FI;
IF instruction pointer is not within code segment limits THEN #GP(0); FI;
SS:ESP  TSS(SS:ESP) (* segment descriptor information also loaded *)
IF 32-bit gate
THEN
ELSE (* 16-bit gate *)
FI;
IF 32-bit gate
THEN
Volume 4: Base IA-32 Instruction Reference
TSSstackAddress  new code segment (DPL  8) + 4
IF (TSSstackAddress + 7)  TSS limit
THEN #TS(current TSS selector); FI;
NewSS  TSSstackAddress + 4;
NewESP  stack address;
TSSstackAddress  new code segment (DPL  4) + 2
IF (TSSstackAddress + 4)  TSS limit
THEN #TS(current TSS selector); FI;
NewESP  TSSstackAddress;
NewSS  TSSstackAddress + 2;
THEN #TS(SS selector + EXT);
THEN #TS(SS selector + EXT);
IF new stack does not have room for 24 bytes (error code pushed)
OR 20 bytes (no error code pushed)
THEN #SS(segment selector + EXT);
FI;
IF new stack does not have room for 12 bytes (error code pushed)
OR 10 bytes (no error code pushed);
THEN #SS(segment selector + EXT);
FI;
CS:EIP  Gate(CS:EIP); (* segment descriptor information also loaded *)
CS:IP  Gate(CS:IP); (* segment descriptor information also loaded *)
Push(far pointer to old stack); (* old SS and ESP, 3 words padded to 4 *);
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