Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1084

mov — Move Processor Status Register
( ) mov
Format: qp r
( ) mov psr.l =
qp
The source operand is copied to the destination register. See
Description:
Status Register (PSR)" on page
For move from processor status register, PSR bits {36:35} and {31:0} are read, and
copied into GR
For move to processor status register, GR
and bits {63:32} are ignored. Bits {31:0} of GR
the PSR must be 0 or a Reserved Register/Field fault will result. An implementation may
also raise Reserved Register/Field fault if bits {63:32} in GR
reserved fields of the PSR are non-zero.
Moves to and from the PSR can only be performed at the most privileged level, and
when PSR.vm is 0.
The contents of the interruption resources (that are overwritten when the PSR.ic bit is
1) are undefined if an interruption occurs between the enabling of the PSR.ic bit and a
subsequent instruction serialize operation.
Operation: if (PR[qp]) {
if (from_form)
check_target_register(r
if (PSR.cpl != 0)
privileged_operation_fault(0);
if (from_form) {
if (PSR.vm == 1)
tmp_val = zero_ext(PSR{31:0}, 32);
tmp_val |= PSR{36:35} << 35;
GR[r
GR[r
} else {
if (GR[r
if (is_reserved_field(PSR_TYPE, PSR_MOVPART, GR[r
if (PSR.vm == 1)
PSR{31:0} = GR[r
}
}
Illegal Operation fault
Interruptions:
Privileged Operation fault
Register NaT Consumption fault
Software must issue an instruction or data serialize operation before issuing
Serialization:
instructions dependent upon the altered PSR bits. Unlike with the rsm instruction, the
PSR.i bit is not treated specially when cleared.
Volume 3: Instruction Reference
= psr
1
r
2
2:23.
. All other bits of the PSR read as zero.
r
1
virtualization_fault();
] = tmp_val;
1
].nat = 0;
1
// to_form
].nat)
2
register_nat_consumption_fault(0);
reserved_register_field_fault();
virtualization_fault();
]{31:0};
2
is read, bits {31:0} copied into PSR{31:0}
r
2
corresponding to reserved fields of
r
2
);
1
// read lower 32 bits
// read mc and it bits
// other bits read as zero
Reserved Register/Field fault
Virtualization fault
mov psr
from_form M36
to_form M35
Section 3.3.2, "Processor
corresponding to
r
2
]))
2
3:185