Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1057

ldf
Table 2-36.
fldtype
Completer
sa
c.nc
c.clr
For more details on speculative, advanced and check loads see
Speculation" on page 1:60
on memory attributes are described in
For the non-speculative load types, if NaT bit associated with GR
Consumption fault is taken. For speculative and speculative advanced loads, no fault is
raised, and the exception is deferred. For the base-update calculation, if the NaT bit
associated with GR
raised.
The value of the ldhint modifier specifies the locality of the memory access. The
mnemonic values of ldhint are given in
implied in the base update forms. The address specified by the value in GR
base update acts as a hint to prefetch the indicated cache line. This prefetch uses the
locality hints specified by ldhint. Prefetch and locality hints do not affect program
functionality and may be ignored by the implementation. See
Hierarchy Control and Consistency" on page 1:69
In the no_base_update form, the value in GR r
implied.
The PSR.mfl and PSR.mfh bits are updated to reflect the modification of FR f
Hardware support for ldfe (10-byte) instructions that reference a page that is neither a
cacheable page with write-back policy nor a NaTPage is optional. On processor models
that do not support such ldfe accesses, an Unsupported Data Reference fault is raised
when an unsupported reference is attempted. The fault is delivered only on the normal,
advanced, and check load flavors. Control-speculative flavors of ldfe always defer the
Unsupported Data Reference fault.
3:158
FP Load Types (Continued)
Interpretation
Speculative An entry is added to the ALAT, and certain exceptions may be deferred.
Advanced load Deferral causes NaTVal to be placed in the target register, and the
processor ensures that no ALAT entry exists for the target register. The
absence of an ALAT entry is later used to detect deferral or collision.
Check load – The ALAT is searched for a matching entry. If found, no load is done
no clear and the target register is unchanged. Regardless of ALAT hit or miss,
base register updates are performed, if specified. An implementation
may optionally cause the ALAT lookup to fail independent of whether an
ALAT entry matches. If not found, a load is performed, and an entry is
added to the ALAT (unless the referenced data page has a
non-speculative attribute, in which case no ALAT entry is allocated).
Check load – clear The ALAT is searched for a matching entry. If found, the entry is
removed, no load is done and the target register is unchanged.
Regardless of ALAT hit or miss, base register updates are performed, if
specified. An implementation may optionally cause the ALAT lookup to
fail independent of whether an ALAT entry matches. If not found, a clear
check load behaves like a normal load.
and Section 4.4.5, "Data Speculation" on page
is 1, the NaT bit associated with GR
r
2
Special Load Operation
Section 4.4, "Memory Attributes" on page
is set to 1 and no fault is
r
3
Table 2-34 on page 3:152. A prefetch hint is
for details.
is not modified and no prefetch hint is
3
Section 4.4.4, "Control
1:63. Details
2:75.
is 1, a Register NaT
r
3
after the
r
3
Section 4.4.6, "Memory
.
1
Volume 3: Instruction Reference