Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1136

If IPSR.is is 1, software must set other IPSR fields properly for IA-32 instruction set
execution; otherwise processor operation is undefined. See
Status Register Fields" on page 2:24
Software must issue a mf instruction before this instruction if memory ordering is
required between IA-32 processor-consistent and Itanium unordered memory
references. The processor does not ensure Itanium-instruction-set-generated writes
into the instruction stream are seen by subsequent IA-32 instructions.
Software must ensure the code segment descriptor and selector are loaded before
issuing this instruction. If the target EIP value exceeds the code segment limit or has a
code segment privilege violation, an IA_32_Exception(GPFault) exception is raised on
the target IA-32 instruction. For entry into 16-bit IA-32 code, if IIP is not within
64K-bytes of CSD.base a GPFault is raised on the target instruction.
EFLAG.rf and PSR.id are unmodified until the successful completion of the target IA-32
instruction. PSR.da, PSR.dd, PSR.ia and PSR.ed are cleared to zero before the target
IA-32 instruction begins execution.
IA-32 instruction set execution leaves the contents of the ALAT undefined. Software can
not rely on ALAT state across an instruction set transition. On entry to IA-32 code,
existing entries in the ALAT are ignored.
Operation:
if (!followed_by_stop())
undefined_behavior();
unimplemented_address = 0;
if (PSR.cpl != 0)
privileged_operation_fault(0);
if (PSR.vm == 1)
virtualization_fault();
taken_rfi = 1;
PSR = CR[IPSR];
if (CR[IPSR].is == 1) {
if (CR[IPSR].ic == 0 || CR[IPSR].dt == 0 ||
CR[IPSR].mc == 1 || CR[IPSR].it == 0)
undefined_behavior();
tmp_IP = CR[IIP];
if (!impl_uia_fault_supported() &&
((CR[IPSR].it && unimplemented_virtual_address(tmp_IP, IPSR.vm))
|| (!CR[IPSR].it && unimplemented_physical_address(tmp_IP))))
unimplemented_address = 1;
EIP{31:0} = CR[IIP]{31:0} - AR[CSD].Base;
rse_restore_frame(0, 0, CFM.sof);
CFM.sof = 0;
CFM.sol = 0;
CFM.sor = 0;
CFM.rrb.gr = 0;
CFM.rrb.fr = 0;
CFM.rrb.pr = 0;
rse_invalidate_non_current_regs();
//The register stack engine is disabled during IA-32
Volume 3: Instruction Reference
for details.
//resume IA-32 instruction set
//compute effective instruction pointer
//force zero-sized restored frame
Table 3-2, "Processor
3:237
rfi