Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1520

INTn/INTO/INT3—Call to Interrupt Procedure (Continued)
Table 2-14.
PE
VM
IOPL
DPL/CPL
RELATIONSHIP
INTERRUPT TYPE
GATE TYPE
REAL-ADDRESS-MODE
PROTECTED-MODE
TRAP-OR-INTERRUPT-G
ATE
INTER-PRIVILEGE-LEVEL
-INTERRUPT
INTRA-PRIVILEGE-LEVE
L-INTERRUPT
INTERRUPT-FROM-VIRT
UAL-8086-MODE
TASK-GATE
#GP
Notes:
 Don't Care
Y Yes, Action Taken
BlankAction Not Taken
When the processor is executing in virtual-8086 mode, the IOPL determines the action
of the INTn instruction. If the IOPL is less than 3, the processor generates a general
protection exception (#GP); if the IOPL is 3, the processor executes a protected mode
interrupt to privilege level 0. The interrupt gate's DPL must be set to three and the
target CPL of the interrupt handler procedure must be 0 to execute the protected mode
interrupt to privilege level 0.
The interrupt descriptor table register (IDTR) specifies the base linear address and limit
of the IDT. The initial base address value of the IDTR after the processor is powered up
or reset is 0.
Operation
The following operational description applies not only to the INTn and INTO
instructions, but also to external interrupts and exceptions.
IF Itanium System EnvironmentTHEN
IF INT3 Form THEN IA_32_Exception(3);
IF INTO Form THEN IA_32_Exception(4);
IF INT Form THEN IA-32_Interrupt(N);
FI;
4:218
INT Cases
0 1 1
– – –
– – –
– DPL< –
CPL
– S/W –
– – Task
Y
Y Y
Y
Y
1 1
– –
– –
DPL> DPL=
CPL CPL or C
– –
Trap or Trap or
Interrupt Interrupt
Y Y
Y Y
Y
Y
Volume 4: Base IA-32 Instruction Reference
1 1
0 1
– <3
DPL< –
CPL & NC
– –
Trap or Trap or
Interrupt Interrupt
Y Y
Y Y
Y
Y
1
1
=3
–
–
Trap or
Interrupt
Y
Y
Y