Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1135

rfi
rfi — Return From Interruption
rfi
Format:
The machine context prior to an interruption is restored. PSR is restored from IPSR,
Description:
IPSR is unmodified, and IP is restored from IIP. Execution continues at the bundle
address loaded into the IP, and the instruction slot loaded into PSR.ri.
This instruction must be immediately followed by a stop; otherwise, operation is
undefined. This instruction switches to the register bank specified by IPSR.bn.
Instructions in the same instruction group that access GR16 to GR31 reference the
previous register bank. Subsequent instruction groups reference the new register bank.
This instruction performs instruction serialization, which ensures:
• prior modifications to processor register resources that affect fetching of
subsequent instruction groups are observed.
• prior modifications to processor register resources that affect subsequent execution
or data memory accesses are observed.
• prior memory synchronization (sync.i) operations have taken effect on the local
processor instruction cache.
• subsequent instruction group fetches (including the target instruction group) are
re-initiated after rfi completes.
The rfi instruction must be in an instruction group after the instruction group
containing the operation that is to be serialized.
This instruction can only be executed at the most privileged level, and when PSR.vm is
0. This instruction can not be predicated.
Execution of this instruction is undefined if PSR.ic or PSR.i are 1. Software must ensure
that an interruption cannot occur that could modify IIP, IPSR, or IFS between when
they are written and the subsequent rfi.
Execution of this instruction is undefined if IPSR.ic is 0 and the current register stack
frame is incomplete.
This instruction does not take Lower Privilege Transfer, Taken Branch or Single Step
traps.
If this instruction sets PSR.ri to 2 and the target is an MLX bundle, then an Illegal
Operation fault will be taken on the target bundle.
If IPSR.is is 1, control is resumed in the IA-32 instruction set at the virtual linear
address specified by IIP{31:0}. PSR.di does not inhibit instruction set transitions for
this instruction. If PSR.dfh is 1 after rfi completes execution, a Disabled FP Register
fault is raised on the target IA-32 instruction.
If IPSR.is is 1 and an Unimplemented Instruction Address trap is taken, IIP will contain
the original 64-bit target IP. (The value will not have been zero extended from 32 bits.)
When entering the IA-32 instruction set, the size of the current stack frame is set to
zero, and all stacked general registers are left in an undefined state. Software can not
rely on the value of these registers across an instruction set transition. Software must
ensure that BSPSTORE==BSP on entry to the IA-32 instruction set, otherwise
undefined behavior may result.
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B8
Volume 3: Instruction Reference