Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1837

MOVMSKPS: Move Mask to Integer
Opcode
0F,50,/r
Operation: r32[3] = xmm[127]; r32[2] = xmm[95];
r32[1] = xmm[63];
r32[7-4] = 0x0; r32[15-8] = 0x00;
r32[31-16] = 0x0000;
The MOVMSKPS instruction returns to the integer register r32 a 4-bit mask formed of
Description:
the most significant bits of each SP FP number of its operand.
None
FP Exceptions:
None.
Numeric Exceptions:
Protected Mode Exceptions:
#UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #MF if there is a pending FPU
exception.; #UD if CRCR4.OSFXSR(bit 9) = 0; #UD if CPUID.XMM(EDX bit 25) = 0.
Real Address Mode Exceptions:
#UD if CR0.EM = 1; #NM if TS bit in CR0 is set.; #UD if CRCR4.OSFXSR(bit 9) = 0;
#UD if CPUID.XMM(EDX bit 25) = 0.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode.
Additional Itanium System Environment Exceptions
Itanium Reg Faults
The usage of Repeat Prefixes (F2H, F3H) with MOVMSKPS is reserved. Different
Comments:
processor implementations may handle this prefix differently. Usage of this prefix with
MOVMSKPS risks incompatibility with future processors.
Volume 4: IA-32 SSE Instruction Reference
Instruction
MOVMSKPS r32, xmm
r32[0] = xmm[31];
Disabled FP Register Fault if PSR.dfl is 1, NaT Register
Consumption Fault
Description
Move the single mask to r32.
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