Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1661

SGDT/SIDT—Store Global/Interrupt Descriptor Table Register
Opcode
0F 01 /0
0F 01 /1
Description
Stores the contents of the global descriptor table register (GDTR) or the interrupt
descriptor table register (IDTR) in the destination operand. The destination operand is a
pointer to 6-byte memory location. If the operand-size attribute is 32 bits, the 16-bit
limit field of the register is stored in the lower 2 bytes of the memory location and the
32-bit base address is stored in the upper 4 bytes. If the operand-size attribute is 16
bits, the limit is stored in the lower 2 bytes and the 24-bit base address is stored in the
third, fourth, and fifth byte, with the sixth byte is filled with 0s.
The SGDT and SIDT instructions are useful only in operating-system software; however,
they can be used in application programs.
Operation
IF Itanium System Environment THEN IA-32_Intercept(INST,SGDT/SIDT);
IF instruction is IDTR
THEN
IF OperandSize = 16
FI;
ELSE (* instruction is SGDT *)
IF OperandSize = 16
FI;
FI;
Flags Affected
None.
Additional Itanium System Environment Exceptions
IA-32_Intercept
Volume 4: Base IA-32 Instruction Reference
Instruction
SGDT m
SIDT m
THEN
DEST[0:15]  IDTR(Limit);
DEST[16:39]  IDTR(Base); (* 24 bits of base address loaded; *)
DEST[40:47]  0;
ELSE (* 32-bit Operand Size *)
DEST[0:15]  IDTR(Limit);
DEST[16:47]  IDTR(Base); (* full 32-bit base address loaded *)
THEN
DEST[0:15]  GDTR(Limit);
DEST[16:39]  GDTR(Base); (* 24 bits of base address loaded; *)
DEST[40:47]  0;
ELSE (* 32-bit Operand Size *)
DEST[0:15]  GDTR(Limit);
DEST[16:47]  GDTR(Base); (* full 32-bit base address loaded *)
Instruction Intercept for SIDT and SGDT.
Description
Store GDTR to m
Store IDTR to m
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