Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1731

PMADDWD—Packed Multiply and Add
Opcode
0F F5 /r
Description
Multiplies the individual signed words of the destination operand by the corresponding
signed words of the source operand, producing four signed, doubleword results (see
Figure 3-12). The two doubleword results from the multiplication of the high-order
words are added together and stored in the upper doubleword of the destination
operand; the two doubleword results from the multiplication of the low-order words are
added together and stored in the lower doubleword of the destination operand. The
destination operand must be an MMX technology register; the source operand may be
either an MMX technology register or a 64-bit memory location.
The PMADDWD instruction wraps around to 80000000H only when all four words of
both the source and destination operands are 8000H.
Figure 3-12.
mm
mm/m64
mm
Operation
DEST(31..0)  (DEST(15..0)  SRC(15..0)) + (DEST(31..16)  SRC(31..16));
DEST(63..32)  (DEST(47..32)  SRC(47..32)) + (DEST(63..48)  SRC(63..48));
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
®
Volume 4: IA-32 Intel MMX™ Technology Instruction Reference
Instruction
PMADDWD mm, mm/m64 Multiply the packed words in mm by the packed words in
Operation of the PMADDWD Instruction
PMADDWD mm, mm/m64
*
+
Abort.
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Description
mm/m64 . Add the 32-bit pairs of results and store in mm
as doubleword
0111000111000111
*
*
1000000000000000
1100100011100011
0111000111000111
*
0000010000000000
+
1001110000000000
4:429