Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1528

INTn/INTO/INT3—Call to Interrupt Procedure (Continued)
Protected Mode Exceptions
#GP(0)
#GP(selector)
#SS(0)
#SS(selector)
#NP(selector)
#TS(selector)
#PF(fault-code)
Real Address Mode Exceptions
#GP
#SS
4:226
If the instruction pointer in the IDT or in the interrupt-, trap-, or task
gate is beyond the code segment limits.
If the segment selector in the interrupt-, trap-, or task gate is null.
If a interrupt-, trap-, or task gate, code segment, or TSS segment
selector index is outside its descriptor table limits.
If the interrupt vector is outside the IDT limits.
If an IDT descriptor is not an interrupt-, trap-, or task-descriptor.
If an interrupt is generated by the INTn instruction and the DPL of
an interrupt-, trap-, or task-descriptor is less than the CPL.
If the segment selector in an interrupt- or trap-gate does not point
to a segment descriptor for a code segment.
If the segment selector for a TSS has its local/global bit set for local.
If a TSS segment descriptor specifies that the TSS is busy or not
available.
If pushing the return address, flags, or error code onto the stack
exceeds the bounds of the stack segment and no stack switch
occurs.
If the SS register is being loaded and the segment pointed to is
marked not present.
If pushing the return address, flags, error code, or stack segment
pointer exceeds the bounds of the stack segment.
If code segment, interrupt-, trap-, or task gate, or TSS is not
present.
If the RPL of the stack segment selector in the TSS is not equal to
the DPL of the code segment being accessed by the interrupt or trap
gate.
If DPL of the stack segment descriptor pointed to by the stack
segment selector in the TSS is not equal to the DPL of the code
segment descriptor for the interrupt or trap gate.
If the stack segment selector in the TSS is null.
If the stack segment for the TSS is not a writable data segment.
If segment-selector index for stack segment is outside descriptor
table limits.
If a page fault occurs.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the interrupt vector is outside the IDT limits.
If stack limit violation on push.
If pushing the return address, flags, or error code onto the stack
exceeds the bounds of the stack segment when a stack switch
occurs.
Volume 4: Base IA-32 Instruction Reference