Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1770

4.6.1.3 Compare Instructions
The CMPPS (Compare packed single-precision floating-point) instruction compares four
pairs of packed single-precision floating-point numbers using the immediate operand as
a predicate, returning per SP field an all "1" 32-bit mask or an all "0" 32-bit mask as a
result. The instruction supports a full set of 12 conditions: equal, less than, less than
equal, greater than, greater than or equal, unordered, not equal, not less than, not less
than or equal, not greater than, not greater than or equal, ordered.
The CMPSS (Compare scalar single-precision floating-point) instruction compares the
least significant pairs of packed single-precision floating-point numbers using the
immediate operand as a predicate (same as CMPPS), returning per SP field an all "1"
32-bit mask or an all "0" 32-bit mask as a result.
The COMISS (Compare scalar single-precision floating-point ordered and set EFLAGS)
instruction compares the least significant pairs of packed single-precision floating-point
numbers and sets the ZF,PF,CF bits in the EFLAGS register (the OF, SF and AF bits are
cleared).
The UCOMISS (Unordered compare scalar single-precision floating-point ordered and
set EFLAGS) instruction compares the least significant pairs of packed single-precision
floating-point numbers and sets the ZF,PF,CF bits in the EFLAGS register as described
above (the OF, SF and AF bits are cleared).
4.6.1.4 Shuffle Instructions
The SHUFPS (Shuffle packed single-precision floating-point) instruction is able to
shuffle any of the packed four single-precision floating-point numbers from one source
operand to the lower two destination fields; the upper two destination fields are
generated from a shuffle of any of the four SP FP numbers from the second source
operand
any combination of the four SP FP numbers from this register.
Figure 4-5.
The UNPCKHPS (Unpacked high packed single-precision floating-point) instruction
performs an interleaved unpack of the high-order data elements of first and second
packed single-precision floating-point operands. It ignores the lower half part of the
4:468
(Figure 4-5). By using the same register for both sources, SHUFPS can return
Packed Shuffle Operation
X4
Y4
{Y4 ... Y1} {Y4 ... Y1}
X3 X2
Y3 Y2
{X4 ... X1}
Volume 4: IA-32 SSE Instruction Reference
X1
Y1
{X4 ... X1}