Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1505

HLT—Halt
Opcode
F4
Description
Stops instruction execution and places the processor in a HALT state. An enabled
interrupt, NMI, or a reset will resume execution. If an interrupt (including NMI) is used
to resume execution after a HLT instruction, the saved instruction pointer (CS:EIP)
points to the instruction following the HLT instruction.
The HLT instruction is a privileged instruction. When the processor is running in
protected or virtual 8086 mode, the privilege level of a program or procedure must to 0
to execute the HLT instruction.
Operation
IF Itanium System Environment THEN IA-32_Intercept(INST,HALT);
Enter Halt state;
Flags Affected
None.
Additional Itanium System Environment Exceptions
IA-32_Intercept
Protected Mode Exceptions
#GP(0)
Real Address Mode Exceptions
None.
Virtual 8086 Mode Exceptions
#GP(0)
Volume 4: Base IA-32 Instruction Reference
Instruction Description
HLT Halt
Mandatory Instruction Intercept.
If the current privilege level is not 0.
If the current privilege level is not 0.
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