Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1567

LGDT/LIDT—Load Global/Interrupt Descriptor Table Register (Continued)
Additional Itanium System Environment Exceptions
IA-32_Intercept
Protected Mode Exceptions
#UD
#GP(0)
#SS(0)
#PF(fault-code)
Real Address Mode Exceptions
#UD
#GP
#SS
Virtual 8086 Mode Exceptions
#UD
#GP(0)
#SS(0)
#PF(fault-code)
Volume 4: Base IA-32 Instruction Reference
Mandatory Instruction Intercept for LIDT and LGDT
If source operand is not a memory location.
If the current privilege level is not 0.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it
contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If source operand is not a memory location.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
If source operand is not a memory location.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
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