Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1882

PREFETCH: Prefetch
Opcode
0F,18,/1
0F,18,/2
0F,18,/3
0F,18,/0
Operation: fetch (m8);
If there are no excepting conditions, the prefetch instruction fetches the line containing
Description:
the addresses byte to a location in the cache hierarchy specified by a locality hint. If the
line is already present in the cache hierarchy at a level closer to the processor, no data
movement occurs. The bits 5:3 of the ModR/M byte specify locality hints as follows:
• Temporal data(t0) - prefetch data into all cache levels.
• Temporal with respect to first level cache (t1) – prefetch data in all cache levels
except 0th cache level.
• Temporal with respect to second level cache (t2) – prefetch data in all cache levels,
except 0th and 1st cache levels.
• Non-temporal with respect to all cache levels (nta) – prefetch data into
non-temporal cache structure.
Locality hints do not affect the functional behavior of the program. They are
implementation dependent, and can be overloaded or ignored by an implementation.
The prefetch instruction does not cause any exceptions (except for code breakpoints),
does not affect program behavior and may be ignored by the implementation. The
amount of data prefetched is implementation dependent. It will however be a minimum
of 32 bytes. Prefetches to uncacheable memory (UC or WC memory types) will be
ignored. Additional ModRM encodings, besides those specified above, are defined to be
reserved and the use of reserved encodings risks future incompatibility.
None
Numeric Exceptions:
Protected Mode Exceptions:
Real Address Mode Exceptions:
Virtual 8086 Mode Exceptions:
Additional Itanium System Environment Exceptions: None
This instruction is merely a hint.If executed, this instruction moves data closer to the
Comments:
processor in anticipation of future use. The performance of these instructions in
application code can be implementation specific. To achieve maximum speedup, code
tuning might be necessary for each implementation. The non temporal hint also
minimizes pollution of useful cache data.
PREFETCH instructions ignore the value of CR4.OSFXSR. Since they do not affect the
new SSE state, they will not generate an invalid exception if CR4.OSFXSR = 0.
4:580
Instruction
PREFETCHT0 m8
PREFETCHT1 m8
PREFETCHT2 m8
PREFETCHNTA m8
None
None
None
Description
Move data specified by address closer to the processor using
the t0 hint.
Move data specified by address closer to the processor using
the t1 hint.
Move data specified by address closer to the processor using
the t2 hint.
Move data specified by address closer to the processor using
the nta hint.
Volume 4: IA-32 SSE Instruction Reference