Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1812

15 14
Rsrvd
Reserved
Reserved
Reserved
Three fields in the floating-point save area contain reserved bits that are not indicated
in the table:
• FOP: The lower 11-bits contain the opcode, upper 5-bits are reserved.
• IP & DP:32-bit mode: 32-bit IP-offset.
• 16-bit mode: lower 16-bits are IP-offset and upper 16-bits are reserved.
If the MXCSR state contains an unmasked exception with corresponding status flag also
set, loading it will not result in a floating-point error condition being asserted; only the
next occurrence of this unmasked exception will result in the error condition being
asserted.
Some bits of MXCSR (bits 31-16 and bit 6) are defined as reserved and cleared;
attempting to write a non-zero value to these bits will result in a general protection
exception.
FXRSTOR does not flush pending x87-FP exceptions, unlike FRSTOR. To check and raise
exceptions when loading a new operating environment, use FWAIT after FXRSTOR.
The SSE fields in the save image (XMM0-XMM7 and MXCSR) may not be loaded into the
processor if the CR4.OSFXSR bit is not set. This CR4 bit must be set in order to enable
execution of SSE instructions.
If #AC exception detection is disabled, a general protection exception is signalled if the
FP Exceptions:
address is not aligned on 16-byte boundary. Note that if #AC is enabled (and CPL is 3),
signalling of #AC is not guaranteed and may vary with implementation; in all
implementations where #AC is not signalled, a general protection fault will instead be
signalled. In addition, the width of the alignment check when #AC is enabled may also
vary with implementation; for instance, for a given implementation #AC might be
signalled for a 2-byte misalignment, whereas #GP might be signalled for all other
misalignments (4/8/16-byte). Invalid opcode exception if instruction is preceded by a
LOCK override prefix. General protection fault if reserved bits of MXCSR are loaded with
non-zero values
None
Numeric Exceptions:
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF (fault-code) for a page
fault; #NM if CR0.EM = 1; #NM if TS bit in CR0 is set; #AC for unaligned memory
reference. To enable #AC exceptions, three conditions must be true(CR0.AM is set;
EFLAGS.AC is set; current CPL is 3).
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #NM if CR0.EM = 1; #NM if TS bit in CR0 is set.
4:510
13 12 11 10 9
CS IP
8 7 6 5 4
FOP FTW
Volume 4: IA-32 SSE Instruction Reference
3 2 1 0
FSW FCW
0
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480
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