Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1879

MASKMOVQ: Byte Mask Write (Continued)
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #MF if there is a
pending FPU exception.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #AC for unaligned memory reference if the
current privilege level is 3; #PF (fault-code) for a page fault.
Additional Itanium System Environment Exceptions
Itanium Reg Faults
MASKMOVQ can be used to improve performance for algorithms which need to merge
Comments:
data on a byte granularity.MASKMOVQ should not cause a read for ownership; doing so
generates unnecessary bandwidth since data is to be written directly using the
byte-mask without allocating old data prior to the store. Similar to the SSE
non-temporal store instructions, MASKMOVQ minimizes pollution of the cache
hierarchy. MASKMOVQ implicitly uses weakly-ordered, write-combining stores (WC).
See Section 4.6.1.9, "Cacheability Control Instructions" for further information about
non-temporal stores.
As a consequence of the resulting weakly-ordered memory consistency model, a
fencing operation such as SFENCE should be used if multiple processors may use
different memory types to read/write the same memory location specified by edi.
This instruction behaves identically to MMX technology instructions, in the presence of
x87-FP instructions: transition from x87-FP to MMX technology (TOS=0, FP valid bits
set to all valid).
MASMOVQ ignores the value of CR4.OSFXSR. Since it does not affect the new SSE
state, they will not generate an invalid exception if CR4.OSFXSR = 0.
Volume 4: IA-32 SSE Instruction Reference
Disabled FP Register Fault if PSR.dfl is 1
4:577