Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1695

XCHG—Exchange Register/Memory with Register
Opcode
90+ rw
90+ rw
90+ rd
90+ rd
86 / r
86 / r
87 / r
87 / r
87 / r
87 / r
Description
Exchanges the contents of the destination (first) and source (second) operands. The
operands can be two general-purpose registers or a register and a memory location.
When the operands are two registers, one of the registers must be the EAX or AX
register. If a memory operand is referenced, the LOCK# signal is automatically asserted
for the duration of the exchange operation, regardless of the presence or absence of
the LOCK prefix or of the value of the IOPL.
This instruction is useful for implementing semaphores or similar data structures for
process synchronization. (See Chapter 5, Processor Management and Initialization, in
the Intel Architecture Software Developer's Manual, Volume 3 for more information on
bus locking.)
The XCHG instruction can also be used instead of the BSWAP instruction for 16-bit
operands.
Operation
IF Itanium System Environment AND External_Atomic_Lock_Required AND DCR.lc
THEN IA-32_Intercept(LOCK,XCHG);
TEMP  DEST
DEST  SRC
SRC  TEMP
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
Volume 4: Base IA-32 Instruction Reference
Instruction Description
XCHG AX, r16 Exchange r16 with AX
XCHG r16 ,AX Exchange r16 with AX
XCHG EAX, r32 Exchange r32 with EAX
XCHG r32 ,EAX Exchange r32 with EAX
XCHG r/m8,r8 Exchange byte register with EA byte
XCHG r8,r/m8 Exchange byte register with EA byte
XCHG r/m16,r16 Exchange r16 with EA word
XCHG r16,r/m16 Exchange r16 with EA word
XCHG r/m32,r32 Exchange r32 with EA doubleword
XCHG r32,r/m32 Exchange r32 with EA doubleword
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
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