Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1187

Table 3-1. Pseudo-code Functions (Continued)
Function
spontaneous_deferral(paddr, size,
border, mattr, otype, hint, *defer)
spontaneous_deferral_enabled()
tlb_access_key(vaddr, itype)
tlb_broadcast_purge(rid, vaddr, size,
type)
tlb_enter_privileged_code()
tlb_grant_permission(vaddr, type, pl)
tlb_insert_data(slot, pte0, pte1, vaddr, rid,
tr)
tlb_insert_inst(slot, pte0, pte1, vaddr, rid,
tr)
tlb_may_purge_dtc_entries(rid, vaddr,
size)
3:288
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Intel Itanium Architecture Software Developer's Manual Rev. 2.3
Implementation-dependent routine which optionally forces *defer to TRUE if all of
the following are true: spontaneous deferral is enabled, spontaneous deferral is
permitted by the programming model, and the processor determines it would be
advantageous to defer the speculative load (e.g., based on a miss in some particular
level of cache).
Implementation-dependent routine which returns TRUE or FALSE, depending on
whether spontaneous deferral of speculative loads is enabled or disabled in the
processor.
This function returns, in bits 31:8, the access key from the TLB for the entry
corresponding to vaddr and itype ; bits 63:32 and 7:0 return 0. If vaddr is an
unimplemented virtual address, or a matching present translation is not found, the
value 1 is returned.
Sends a broadcast purge DTC and ITC transaction to other processors in the
multiprocessor coherency domain, where the region identifier ( rid ), virtual address
( vaddr ) and page size ( size ) specify the translation entry to purge. The operation
waits until all processors that receive the purge have completed the purge operation.
The purge type ( type ) specifies whether the ALAT on other processors should also
be purged in conjunction with the TC.
This function determines the new privilege level for epc from the TLB entry for the
page containing this instruction. If the page containing the epc instruction has
execute-only page access rights and the privilege level assigned to the page is higher
than (numerically less than) the current privilege level, then the current privilege level
is set to the privilege level field in the translation for the page containing the epc
instruction.
Returns a boolean indicating if read, write access is granted for the specified virtual
memory address ( vaddr ) and privilege level ( pl ). The access type ( type ) specifies
either read or write. The following faults are checked::
• Data Nested TLB fault
• Alternate Data TLB fault
• VHPT Data fault
• Data TLB fault
• Data Page Not Present fault
• Data NaT Page Consumption fault
• Data Key Miss fault
If a fault is generated, this function does not return.
Inserts an entry into the DTLB, at the specified slot number. pte0 , pte1 compose
the translation. vaddr and rid specify the virtual address and region identifier for the
translation. If tr is true the entry is placed in the TR section, otherwise the TC
section.
Inserts an entry into the ITLB, at the specified slot number. pte0 , pte1 compose
the translation. vaddr and rid specify the virtual address and region identifier for the
translation. If tr is true, the entry is placed in the TR section, otherwise the TC
section.
May locally purge DTC entries that match the specified virtual address ( vaddr ),
region identifier ( rid ) and page size ( size ). May also invalidate entries that partially
overlap the parameters. The extent of purging is implementation dependent. If the
purge size is not supported, an implementation may generate a machine check abort
or over purge the translation cache up to and including removal of all entries from the
translation cache.
Operation
Volume 3: Pseudo-Code Functions