Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1822

MAXPS: Packed Single-FP Maximum (Continued)
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #XM for an
unmasked SSE numeric exception (CR4.OSXMMEXCPT =1); #UD for an unmasked SSE
numeric exception (CR4.OSXMMEXCPT =0); #UD if CRCR4.OSFXSR(bit 9) = 0; #UD if
CPUID.XMM(EDX bit 25) = 0.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault.
Additional Itanium System Environment Exceptions
Itanium Reg Faults
Itanium Mem Faults VHPT Data Fault, Data TLB Fault, Alternate Data TLB Fault, Data
Note that if only one source is a NaN for these instructions, the Src2 operand (either
Comments:
NaN or real value) is written to the result; this differs from the behavior for other
instructions as defined in
regardless of which source operand contains the NaN. This approach for MAXPS allows
compilers to use the MAXPS instruction for common C conditional constructs. If instead
of this behavior, it is required that the NaN source operand be returned, the min/max
functionality can be emulated using a sequence of instructions: comparison followed by
AND, ANDN and OR.
4:520
Disabled FP Register Fault if PSR.dfl is 1, NaT Register
Consumption Fault
Page Not Present Fault, Data NaT Page Consumption Abort, Data
Key Miss Fault, Data Key Permission Fault, Data Access Rights
Fault, Data Access Bit Fault
Table 4-3, which is to always write the NaN to the result,
Volume 4: IA-32 SSE Instruction Reference