Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1785

4.9 Instruction Formats
The nature of the Intel SSE architecture allows the use of existing instruction formats.
Instructions use the ModR/M format and are preceded by the 0F prefix byte. In general,
operations are not duplicated to provide two directions (i.e. separate load and store
variants).
4.10 Instruction Prefixes
The SSE instructions use prefixes as specified in
The effect of multiple prefixes (more than one prefix from a group) is unpredictable and
may vary from processor to processor.
Applying a prefix, in a manner not defined in this document, is considered reserved
behavior. For example,
however, the application of a prefix (Repeat, Repeat NE, Operand Size) is reserved for
the following instructions:
ANDPS, ANDNPS, COMISS, FXRSTOR, FXSAVE, ORPS, LDMXCSR, MOVAPS, MOVHPS,
MOVLPS, MOVMSKPS, MOVNTPS, MOVUPS, SHUFPS, STMXCSR, UCOMISS, UNPCKHPS,
UNPCKLPS, XORPS.
Table 4-6.
Prefix Type
Address Size Prefix (67H)
Operand Size (66H)
Segment Override
(2EH,36H,3EH,26H,64H,65H)
Repeat Prefix (F3H)
Repeat NE Prefix(F2H)
Lock Prefix (0F0H)
Table 4-7.
Prefix Type
Address Size Prefix (67H)
Operand Size (66H)
Segment Override
(2EH,36H,3EH,26H,64H,65H)
Repeat Prefix (F3H)
Repeat NE Prefix(F2H)
Lock Prefix (0F0H)
Table 4-8.
Prefix Type
Address Size Prefix (67H)
Operand Size (66H)
Volume 4: IA-32 SSE Instruction Reference
Table 4-6 shows general behavior for most SSE instructions;
SSE Instruction Behavior with Prefixes
Effect on SSE Instructions
Affects SSE instructions with memory operand
Ignored by SSE instructions without memory operand.
Reserved and may result in unpredictable behavior.
Affects SSE instructions with mem.operand
Ignored by SSE instructions without mem operand
Affects SSE instructions
Reserved and may result in unpredictable behavior.
Generates invalid opcode exception.
SIMD Integer Instructions – Behavior with Prefixes
Effect on Intel
Affects Intel MMX technology instructions with mem. operand
Ignored by Intel MMX technology instructions without mem. operand.
Reserved and may result in unpredictable behavior.
Affects Intel MMX technology instructions with mem. operand
Ignored by Intel MMX technology instructions without mem operand
Reserved and may result in unpredictable behavior.
Reserved and may result in unpredictable behavior.
Generates invalid opcode exception.
Cacheability Control Instruction Behavior with Prefixes
Effect on SSE Instructions
Affects cacheability control instruction with a mem. operand
Ignored by cacheability control instruction w/o a mem. operand.
Reserved and may result in unpredictable behavior.
Table 4-6, Table 4-7, and
® ™
MMX Technology Instructions
Table 4-8.
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