Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1635

RDPMC—Read Performance-Monitoring Counters
Opcode
0F 33
Description
Loads the contents of the N-bit performance-monitoring counter specified in the ECX
register into registers EDX:EAX. The EDX register is loaded with the high-order N-32
bits of the counter and the EAX register is loaded with the low-order 32 bits.
The RDPMC instruction allows application code running at a privilege level of 1, 2, or 3
to read the performance-monitoring counters if the PCE flag in the CR4 register is set
for IA-32 System Environment operation or in the Itanium System Environment if the
performance counters have been configured as user level counters. This instruction is
provided to allow performance monitoring by application code without incurring the
overhead of a call to an operating-system procedure.
The performance-monitoring counters are event counters that can be programmed to
count events such as the number of instructions decoded, number of interrupts
received, or number of cache loads.
The RDPMC instruction does not serialize instruction execution. That is, it does not
imply that all the events caused by the preceding instructions have been completed or
that events caused by subsequent instructions have not begun. If an exact event count
is desired, software must use a serializing instruction (such as the CPUID instruction)
before and/or after the execution of the RDPCM instruction.
The RDPMC instruction can execute in 16-bit addressing mode or virtual 8086 mode;
however, the full contents of the ECX register are used to determine the counter to
access and a full N-bit result is returned (the low-order 32 bits in the EAX register and
the high-order N-32 bits in the EDX register).
Operation
IF (ECX != Implemented Counters) THEN #GP(0)
IF (Itanium System Environment)
THEN
SECURED = PSR.sp || CR4.pce==0;
IF ((PSR.cpl ==0) || (PSR.cpl!=0 && ~PMC[ECX].pm && ~SECURED)))
THEN
ELSE
FI;
ELSE
IF ((CR4.PCE = 1 OR ((CR4.PCE = 0 ) AND (CPL=0)))
THEN
ELSE (* CR4.PCE is 0 and CPL is 1, 2, or 3 *)
FI;
Volume 4: Base IA-32 Instruction Reference
Instruction
RDPMC
EDX:EAX  PMD[ECX+4];
#GP(0)
EDX:EAX  PMD[ECX+4];
#GP(0)
Description
Read performance-monitoring counter specified by ECX into
EDX:EAX
4:333