Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1890

INDEX
FWAIT Instruction 4:386
fwb Instruction 3:141
FXAM Instruction 4:193
FXCH Instruction 4:195
fxor Instruction 3:142
FXRSTOR Instruction 4:509
FXSAVE Instruction 4:512, 4:515
FXTRACT Instruction 4:197
FYL2X Instruction 4:199
FYL2XP1 Instruction 4:201
G
General Register (GR) 1:25, 1:139
getf Instruction 3:143
GR (General Register) 1:139
H
hint Instruction 3:145
HLT Instruction 4:203
I
I/O Architecture 2:615
IA-32
IA-32 Application Execution 1:109
IA-32 Applications 2:239, 2:595
IA-32 Architecture 1:7, 1:21
IA-32 Current Privilege Level (PSR.cpl) 2:243
IA-32 EFLAG Register 1:123, 2:243
IA-32 Exception
Alignment Check Fault 2:229
Code Breakpoint Fault 2:215
Data Breakpoint,
Branch Trap 2:216
Device Not Available Fault 2:221
Divide Fault 2:214
Double Fault 2:222
General Protection Fault 2:226
INT 3 Trap 2:217
Invalid Opcode Fault 2:220
Invalid TSS Fault 2:223
Machine Check 2:230
Overflow Trap 2:218
Page Fault 2:227
Pending Floating-point Error 2:228
Segment Not Present Fault 2:224
SSE Numeric Error Fault 2:231
Stack Fault 2:225
IA-32 Execution Layer 1:109
IA-32 Floating-point Control Registers 1:126
IA-32 Instruction Reference 4:11
IA-32 Instruction Set 2:253
IA-32 Intel® MMX™ Technology 1:129
IA-32 Intercept
Gate Intercept Trap 2:235
Instruction Intercept Fault 2:233
Index:4
Single Step, Taken
Locked Data Reference Fault 2:237
System Flag Trap 2:236
IA-32 Interrupt
Software Trap 2:232
IA-32 Interruption 2:111
IA-32 Interruption Vector Definitions 2:213
IA-32 Interruption Vector Descriptions 2:213
IA-32 Memory Ordering 2:265
IA-32 Physical Memory References 2:262
IA-32 SSE Extensions 1:20, 1:130
IA-32 System Registers 2:246
IA-32 System Segment Registers 2:241
IA-32 Trap Code 2:213
IA-32 Virtual Memory References 2:261
IBR (Index Breakpoint Register) 2:151, 2:152
IDIV Instruction 4:204
IFA (interuption Faulting Address) 2:541
IFS (Interruption Function State) 2:541
IHA (Interruption Hash Address) 2:41, 2:541
IIB0 (Interruption Instruction Bundle 0) 2:541
IIB1 (Interruption Instruction Bundle 1) 2:541
IIM (Interruption Immediate) 2:541
IIP (Interruption Instruction Pointer) 2:541
IIPA (Interruption Instruction Previous Address)
2:541
Implicit Prefetch 1:70
IMUL Instruction 4:207
IN Instruction 4:210
INC Instruction 4:212
In-flight Resources 2:19
INIT (Initialization Event) 2:96, 2:306, 2:635
Initialization Event (INIT) 2:96
INS Instruction 4:214
INSB Instruction 4:214
INSD Instruction 4:214
Instruction Breakpoint Register (IBR) 2:151,
2:152
Instruction Debug Faults 2:151
Instruction Dependencies 1:148
Instruction Encoding 1:38
Instruction Formats 3:293
SSE 4:483
Instruction Group 1:40
Instruction Level Parallelism 1:15
Instruction Pointer (IP) 1:27, 1:140
Instruction Scheduling 1:148, 1:150, 1:164
Instruction Serialization 2:18
Instruction Set Architecture (ISA) 1:7
Instruction Set Modes 1:110
Instruction Set Transition 1:14
Instruction Set Transitions 2:239, 2:596
Instruction Slot Mapping 1:38
Instruction Slots 1:38
INSW Instruction 4:214
INT (External Interrupt) 2:96
INT3 Instruction 4:217
Index for Volumes 1, 2, 3 and 4