Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1089

mux
mux — Mux
( ) mux1
Format: qp
( ) mux2
qp
A permutation is performed on the packed elements in a single source register, GR
Description:
and the result is placed in GR
permutations can be specified. The five possible permutations are given in
and shown in
Table 2-41.
mbtype
@rev
@mix
@shuf
@alt
@brcst
Figure 2-26.
GR r :
2
GR r :
1
GR r :
2
GR r :
1
3:190
= ,
r r mbtype
1 2 4
= ,
r r mhtype
1 2 8
. For 8-bit elements, only some of all possible
r
1
Figure 2-26.
Mux Permutations for 8-bit Elements
4
Reverse the order of the bytes
Perform a Mix operation on the two halves of GR r
Perform a Shuffle operation on the two halves of GR r
Perform an Alternate operation on the two halves of GR r
Perform a Broadcast operation on the least significand byte of GR r
Mux1 Operation (8-bit elements)
mux1 r1 = r2, @rev
mux1 r1 = r2, @shuf
GR r :
2
GR r :
1
Function
2
2
2
GR r :
2
GR r :
1
mux1 r1 = r2, @mix
GR r :
2
GR r :
1
mux1 r1 = r2, @alt
mux1 r1 = r2, @brcst
one_byte_form
two_byte_form
,
r
2
Table 2-41
2
Volume 3: Instruction Reference
I3
I4