Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1763

PXOR—Logical Exclusive OR
Opcode
0F EF /r
Description
Performs a bitwise logical exclusive-OR (XOR) operation on the quadword source
(second) and destination (first) operands and stores the result in the destination
operand location (see
register or a quadword memory location; the destination operand must be an MMX
technology register. Each bit of the result is 1 if the corresponding bits of the two
operands are different; each bit is 0 if the corresponding bits of the operands are the
same.
Figure 3-24.
mm
mm/m64
mm
Operation
DEST  DEST XOR SRC;
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
®
Volume 4: IA-32 Intel MMX™ Technology Instruction Reference
Instruction
PXOR mm, mm/m64
Figure 3-24). The source operand can be an MMX technology
Operation of the PXOR Instruction
PXOR mm, mm/m64
1111111111111000000000000000010110110101100010000111011101110111
0001000011011001010100000011000100011110111011110001010110010101
1110111100100001010100000011010010101011011001110110001011100010
Abort.
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Description
XOR quadword from mm/m64 to quadword in mm .
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