Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1894
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INDEX
PAL_VPS_RESUME_HANDLER 2:492
PAL_VPS_RESUME_NORMAL 2:489
PAL_VPS_SAVE 2:500
PAL_VPS_SET_PENDING_INTERRUPT 2:495
PAL_VPS_SYNC_READ 2:493
PAL_VPS_SYNC_WRITE 2:494
PAL_VPS_THASH 2:497
PAL_VPS_TTAG 2:498
PAL-based Interruptions 2:95, 2:537
PALE_CHECK 2:282, 2:296
PALE_INIT 2:282, 2:306
PALE_PMI 2:282, 2:310
PALE_RESET 2:282, 2:289
PAND Instruction 4:419
PANDN Instruction 4:421
Parallel Arithmetic 1:79
Parallel Compares 1:172
Parallel Shifts 1:81
pavg Instruction 3:201
PAVGB Instruction 4:563
pavgsub Instruction 3:204
PAVGW Instruction 4:563
pcmp Instruction 3:206
PCMPEQB Instruction 4:423
PCMPEQD Instruction 4:423
PCMPEQW Instruction 4:423
PCMPGTB Instruction 4:426
PCMPGTD Instruction 4:426
PCMPGTW Instruction 4:426
Performance Monitor Data Register (PMD) 1:33
Performance Monitor Events 2:162
Performance Monitoring 2:155, 2:619
Performance Monitoring Vector 2:126
PEXTRW Instruction 4:565
PFS (Previous Function State Register) 1:32
Physical Addressing 2:73
PIB (Processor Interrupt Block) 2:127
PINSRW Instruction 4:566
PKR (Protection Key Register) 2:564
Platform Management Interrupt (PMI) 2:96,
2:310, 2:538, 2:637
PMADDWD Instruction 4:429
pmax Instruction 3:209
PMAXSW Instruction 4:567
PMAXUB Instruction 4:568
PMC (Performance Monitor Configuration) 2:155
PMD (Performance Monitor Data Register) 1:33
PMD (Performance Monitor Data) 2:155
PMI (Platform Management Interrupt) 2:96,
2:310, 2:538, 2:637
pmin Instruction 3:211
PMINSW Instruction 4:569
PMINUB Instruction 4:570
PMOVMSKB Instruction 4:571
pmpy Instruction 3:213
pmpyshr Instruction 3:214
Index:8
PMULHUW Instruction 4:572
PMULHW Instruction 4:431
PMULLW Instruction 4:433
PMV (Performance Monitoring Vector) 2:126
POP Instruction 4:311
POPA Instruction 4:315
POPAD Instruction 4:315
popcnt Instruction 3:216
POPF Instruction 4:317
POPFD Instruction 4:317
POR Instruction 4:435
Power Management 2:313
Power-on Event 2:351
PR (Predicate Register) 1:26, 1:140
Predicate Register (PR) 1:26, 1:140
Predication 1:17, 1:54, 1:143, 1:163, 1:164
Prefetch Hints 1:176
PREFETCH Instruction 4:580
Preserved Values 2:351
Previous Function State (PFS) 1:32
Privilege Level Transfer 1:84
Privilege Levels 2:17
probe Instruction 3:217
Procedure Calls 2:549
Processor Abstraction Layer - See PAL (Processor
Abstraction Layer)
Processor Abstraction Layer (PAL) 2:279
Processor Boot Flow 2:623
Processor Identification Registers (CPUID) 1:34
Processor Interrupt Block (PIB) 2:127
Processor Min-state Save Area 2:302
Processor Reset 2:95
Processor State Parameter (PSP) 2:299, 2:308
Processor Status Register (PSR) 2:23
Programmed I/O 2:534
Protection Keys 2:59, 2:564
psad Instruction 3:220
PSADBW Instruction 4:573
Pseudo-Code Functions 3:281
pshl Instruction 3:222
pshladd Instruction 3:223
pshr Instruction 3:224
pshradd Instruction 3:226
PSHUFW Instruction 4:575
PSLLD Instruction 4:437
PSLLQ Instruction 4:437
PSLLW Instruction 4:437
PSP (Processor State Parameter) 2:308
PSR (Processor Status Register) 2:23
PSRAD Instruction 4:440
PSRAW Instruction 4:440
PSRLD Instruction 4:443
PSRLQ Instruction 4:443
PSRLW Instruction 4:443
psub Instruction 3:227
PSUBB Instruction 4:446
Index for Volumes 1, 2, 3 and 4
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