Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1622

PUSH—Push Word or Doubleword Onto the Stack
Opcode
FF /6
FF /6
50+ rw
50+ rd
6A
68
68
0E
16
1E
06
0F A0
0F A8
Description
Decrements the stack pointer and then stores the source operand on the top of the
procedure stack. The current address-size attribute for the stack segment and the
operand-size attribute determine the amount the stack pointer is decremented (see the
"Operation" below). For example, if 32-bit addressing and operands are being used, the
ESP register (stack pointer) is decremented by 4 and, if 16-bit addressing and operands
are being used, the SP register (stack pointer for 16-bit addressing) is decremented by
2. Pushing 16-bit operands when the stack address-size attribute is 32 can result in a
misaligned the stack pointer (that is, the stack pointer not aligned on a doubleword
boundary).
The PUSH ESP instruction pushes the value of the ESP register as it existed before the
instruction was executed. Thus, if a PUSH instruction uses a memory operand in which
the ESP register is used as a base register for computing the operand address, the
effective address of the operand is computed before the ESP register is decremented.
In the real-address mode, if the ESP or SP register is 1 when the PUSH instruction is
executed, the processor shuts down due to a lack of stack space. No exception is
generated to indicate this condition.
Operation
IF StackAddrSize = 32
THEN
IF OperandSize = 32
THEN
ELSE (* OperandSize = 16*)
FI;
ELSE (* StackAddrSize = 16*)
4:320
Instruction
PUSH r/m16
PUSH r/m32
PUSH r16
PUSH r32
PUSH imm8
PUSH imm16
PUSH imm32
PUSH CS
PUSH SS
PUSH DS
PUSH ES
PUSH FS
PUSH GS
ESP  ESP  4;
SS:ESP  SRC; (* push doubleword *)
ESP  ESP  2;
SS:ESP  SRC; (* push word *)
Description
Push r/m16
Push r/m32
Push r16
Push r32
Push imm8
Push imm16
Push imm32
Push CS
Push SS
Push DS
Push ES
Push FS
Push GS
Volume 4: Base IA-32 Instruction Reference