Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1693

XADD—Exchange and Add
Opcode
0F C0/r
0F C1/r
0F C1/r
Description
Exchanges the first operand (destination operand) with the second operand (source
operand), then loads the sum of the two values into the destination operand. The
destination operand can be a register or a memory location; the source operand is a
register.
This instruction can be used with a LOCK prefix.
Operation
IF Itanium System Environment AND External_Bus_Lock_Required AND DCR.lc
THEN IA-32_Intercept(LOCK,XADD);
TEMP  SRC + DEST
SRC  DEST
DEST  TEMP
Flags Affected
The CF, PF, AF, SF, ZF, and OF flags are set according to the result stored in the
destination operand.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
IA-32_Intercept
Protected Mode Exceptions
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Volume 4: Base IA-32 Instruction Reference
Instruction Description
XADD r/m8,r8 Exchange r8 and r/m8 ; load sum into r/m8 .
XADD r/m16,r16 Exchange r16 and r/m16 ; load sum into r/m16 .
XADD r/m32,r32 Exchange r32 and r/m32 ; load sum into r/m32 .
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Lock Intercept If an external atomic bus lock is required to
–
complete this operation and DCR.lc is 1, no atomic transaction
occurs, this instruction is faulted and an IA-32_Intercept(Lock) fault
is generated. The software lock handler is responsible for the
emulation of this instruction.
If the destination is located in a nonwritable segment.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
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