Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1556

LAR—Load Access Rights Byte (Continued)
Protected Mode Exceptions
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Real Address Mode Exceptions
#UD
Virtual 8086 Mode Exceptions
#UD
4:254
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it
contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3. (Only occurs
when fetching target from memory.)
The LAR instruction is not recognized in real address mode.
The LAR instruction cannot be executed in virtual 8086 mode.
Volume 4: Base IA-32 Instruction Reference