Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1606

OR—Logical Inclusive OR
Opcode
0C ib
0D iw
0D id
80 /1 ib
81 /1 iw
81 /1 id
83 /1 ib
83 /1 ib
08 / r
09 / r
09 / r
0A / r
0B / r
0B / r
Description
Performs a bitwise OR operation on the destination (first) and source (second)
operands and stores the result in the destination operand location. The source operand
can be an immediate, a register, or a memory location; the destination operand can be
a register or a memory location.
Operation
DEST  DEST OR SRC;
Flags Affected
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result.
The state of the AF flag is undefined.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
4:304
Instruction Description
OR AL, imm8 AL OR imm8
OR AX, imm16 AX OR imm16
OR EAX, imm32 EAXOR imm32
OR r/m8,imm8 r/m8 OR imm8
OR r/m16,imm16
OR r/m32,imm32
OR r/m16,imm8 r/m16 OR imm8
OR r/m32,imm8 r/m32 OR imm8
OR r/m8,r8 r/m8 OR r8
OR r/m16,r16 r/m16 OR r16
OR r/m32,r32 r/m32 OR r32
OR r8,r/m8 r8 OR r/m8
OR r16,r/m16 r16 OR r/m16
OR r32,r/m32 r32 OR r/m32
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
r/m16 OR imm16
r/m32 OR imm32
Volume 4: Base IA-32 Instruction Reference