Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1637

RDTSC—Read Time-Stamp Counter
Opcode
0F 31
Description
Loads the current value of the processor's time-stamp counter into the EDX:EAX
registers. The time-stamp counter is contained in a 64-bit MSR. The high-order 32 bits
of the MSR are loaded into the EDX register, and the low-order 32 bits are loaded into
the EAX register. The processor increments the time-stamp counter MSR every clock
cycle and resets it to 0 whenever the processor is reset.
In the IA-32 System Environment, the time stamp disable (TSD) flag in register CR4
restricts the use of the RDTSC instruction. When the TSD flag is clear, the RDTSC
instruction can be executed at any privilege level; when the flag is set, the instruction
can only be executed at privilege level 0. The time-stamp counter can also be read with
the RDMSR instruction.
In the Itanium System Environment, PSR.si and CR4.TSD restricts the use of the
RDTSC instruction. When PSR.si is clear and CR4.TSD is clear, the RDTSC instruction
can be executed at any privilege level; when PSR.si is set or CR4.TSD is set, the
instruction can only be executed at privilege level 0.
The RDTSC instruction is not serializing instruction. Thus, it does not necessarily wait
until all previous instructions have been executed before reading the counter. Similarly,
subsequent instructions may begin execution before the read operation is performed.
This instruction was introduced into the Intel architecture in the Pentium processor.
Operation
IF (IA-32 System Environement)
IF (CR4.TSD = 0) OR ((CR4.TSD = 1) AND (CPL=0))
THEN
ELSE (* CR4 is 1 and CPL is 1, 2, or 3 *)
FI;
ELSE /*Itanium System Environment*/
SECURED = PSR.si || CR4.TSD;
IF (!SECURED) OR (SECURED AND (CPL=0))
THEN
ELSE (* CR4 is 1 and CPL is 1, 2, or 3 *)
FI;
FI;
Flags Affected
None.
Volume 4: Base IA-32 Instruction Reference
Instruction
RDTSC
EDX:EAX  TimeStampCounter;
#GP(0)
EDX:EAX  TimeStampCounter;
#GP(0)
Description
Read time-stamp counter into EDX:EAX
4:335