Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1723

PANDN—Logical AND NOT
Opcode
0F DF /r
Description
Performs a bitwise logical NOT on the quadword destination operand (first operand).
Then, the instruction performs a bitwise logical AND operation on the inverted
destination operand and the quadword source operand (second operand). (See
Figure 3-9.) Each bit of the result of the AND operation is set to one if the
corresponding bits of the source and inverted destination bits are one; otherwise it is
set to zero. The result is stored in the destination operand location.
The source operand can be an MMX technology register or a quadword memory
location; the destination operand must be an MMX technology register.
Figure 3-9.
PANDN mm, mm/m64
mm
m/m64
mm
Operation
DEST (NOT DEST) AND SRC;
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
®
Volume 4: IA-32 Intel MMX™ Technology Instruction Reference
Instruction Description
PANDN mm, mm/m64 AND quadword from mm/m64 to NOT quadword in mm .
Operation of the PANDN Instruction
11111111111110000000000000000101101101010011101111000100010001000
11111111111110000000000000000101101101010011101111000100010001000
11111111111110000000000000000101101101010011101111000100010001000
Abort.
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
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