Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1004

Operation: if (PR[qp]) {
fp_check_target_register(f
if (tmp_isrcode = fp_reg_disabled(f
disabled_fp_register_fault(tmp_isrcode, 0);
if (fp_is_natval(FR[f
FR[f
fp_update_psr(f
} else {
tmp_default_result_pair = fpcvt_exception_fault_check(f
if (fp_raise_fault(tmp_fp_env))
if (fp_is_nan(tmp_default_result_pair.hi)) {
} else {
}
if (fp_is_nan(tmp_default_result_pair.lo)) {
} else {
}
FR[f
FR[f
FR[f
fp_update_fpsr(sf, tmp_fp_env);
fp_update_psr(f
if (fp_raise_traps(tmp_fp_env))
}
}
Invalid Operation (V)
FP Exceptions:
Denormal/Unnormal Operand (D)
Software Assist (SWA) Fault
Volume 3: Instruction Reference
);
1
])) {
2
] = NATVAL;
1
);
1
fp_exception_fault(fp_decode_fault(tmp_fp_env));
tmp_res_hi = INTEGER_INDEFINITE_32_BIT;
tmp_res = fp_ieee_rnd_to_int_sp(fp_reg_read_hi(f
if (tmp_res.exponent)
tmp_res.significand = fp_U64_rsh(
tmp_res.significand, (FP_INTEGER_EXP - tmp_res.exponent));
if (signed_form && tmp_res.sign)
tmp_res.significand = (~tmp_res.significand) + 1;
tmp_res_hi = tmp_res.significand{31:0};
tmp_res_lo = INTEGER_INDEFINITE_32_BIT;
tmp_res = fp_ieee_rnd_to_int_sp(fp_reg_read_lo(f
if (tmp_res.exponent)
tmp_res.significand = fp_U64_rsh(
tmp_res.significand, (FP_INTEGER_EXP - tmp_res.exponent));
if (signed_form && tmp_res.sign)
tmp_res.significand = (~tmp_res.significand) + 1;
tmp_res_lo = tmp_res.significand{31:0};
].significand = fp_concatenate(tmp_res_hi, tmp_res_lo);
1
].exponent = FP_INTEGER_EXP;
1
].sign = FP_SIGN_POSITIVE;
1
);
1
fp_exception_trap(fp_decode_trap(tmp_fp_env));
, f , 0, 0))
1 2
signed_form, trunc_form, sf, &tmp_fp_env);
&tmp_fp_env);
&tmp_fp_env);
Inexact (I)
fpcvt.fx
,
2
), HIGH,
2
), LOW,
2
3:105