Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1830

MOVAPS: Move Aligned Four Packed Single-FP (Continued)
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #UD if CRCR4.OSFXSR(bit 9) =
0; #UD if CPUID.XMM(EDX bit 25) = 0.
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #UD if
CRCR4.OSFXSR(bit 9) = 0; #UD if CPUID.XMM(EDX bit 25) = 0.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault.
Additional Itanium System Environment Exceptions
Itanium Reg Faults
Itanium Mem Faults VHPT Data Fault, Data TLB Fault, Alternate Data TLB Fault, Data
MOVAPS should be used when dealing with 16-byte aligned SP FP numbers. If the data
Comments:
is not known to be aligned, MOVUPS should be used instead of MOVAPS. The usage of
this instruction should be limited to the cases where the aligned restriction is easy to
meet. Processors that support the Intel SSE architecture will provide optimal aligned
performance for the MOVAPS instruction.
The usage of Repeat Prefixes (F2H, F3H) with MOVAPS is reserved. Different processor
implementations may handle this prefix differently. Usage of this prefix with MOVAPS
risks incompatibility with future processors.
4:528
Disabled FP Register Fault if PSR.dfl is 1, NaT Register
Consumption Fault
Page Not Present Fault, Data NaT Page Consumption Abort, Data
Key Miss Fault, Data Key Permission Fault, Data Access Rights
Fault, Data Access Bit Fault
Volume 4: IA-32 SSE Instruction Reference