Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1051

ld
Table 2-33.
ldtype
Completer
sa
c.nc
c.clr
c.clr.acq
acq
bias
For more details on ordered, biased, speculative, advanced and check loads see
Section 4.4.4, "Control Speculation" on page 1:60
Speculation" on page
"Memory Access Ordering" on page
Control and Consistency" on page 1:69
attributes are described in
For the non-speculative load types, if NaT bit associated with GR
Consumption fault is taken. For speculative and speculative advanced loads, no fault is
raised, and the exception is deferred. For the base-update calculation, if the NaT bit
associated with GR
raised.
The value of the ldhint completer specifies the locality of the memory access. The values
of the ldhint completer are given in
update forms. The address specified by the value in GR
a hint to prefetch the indicated cache line. This prefetch uses the locality hints specified
by ldhint. Prefetch and locality hints do not affect program functionality and may be
ignored by the implementation. See
Consistency" on page 1:69
Table 2-34. Load Hints
ldhint Completer
3:152
Load Types (Continued)
Interpretation
Speculative An entry is added to the ALAT, and certain exceptions may be deferred.
Advanced load Deferral causes the target register's NaT bit to be set, and the
processor ensures that no ALAT entry exists for the target register. The
absence of an ALAT entry is later used to detect deferral or collision.
Check load The ALAT is searched for a matching entry. If found, no load is done
– no clear and the target register is unchanged. Regardless of ALAT hit or miss,
base register updates are performed, if specified. An implementation
may optionally cause the ALAT lookup to fail independent of whether an
ALAT entry matches. If not found, a load is performed, and an entry is
added to the ALAT (unless the referenced data page has a
non-speculative attribute, in which case no ALAT entry is allocated).
Check load The ALAT is searched for a matching entry. If found, the entry is
– clear removed, no load is done and the target register is unchanged.
Regardless of ALAT hit or miss, base register updates are performed, if
specified. An implementation may optionally cause the ALAT lookup to
fail independent of whether an ALAT entry matches. If not found, a clear
check load behaves like a normal load.
Ordered check load This type behaves the same as the unordered clear form, except that
– clear the ALAT lookup (and resulting load, if no ALAT entry is found) is
performed with acquire semantics.
Ordered load An ordered load is performed with acquire semantics.
Biased load A hint is provided to the implementation to acquire exclusive ownership
of the accessed cache line.
1:63. For more details on ordered loads see
1:73. See
Section 4.4, "Memory Attributes" on page
is 1, the NaT bit associated with GR
r
2
Table
Section 4.4.6, "Memory Hierarchy Control and
for details.
none Temporal locality, level 1
Special Load Operation
and Section 4.4.5, "Data
Section 4.4.6, "Memory Hierarchy
for details on biased loads. Details on memory
is set to 1 and no fault is
r
3
2-34. A prefetch hint is implied in the base
after the base update acts as
r
3
Interpretation
Volume 3: Instruction Reference
Section 4.4.7,
2:75.
is 1, a Register NaT
r
3