Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1441

FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load
Constant
Opcode
D9 E8
D9 E9
D9 EA
D9 EB
D9 EC
D9 ED
D9 EE
Description
Push one of seven commonly-used constants (in extended-real format) onto the FPU
register stack. The constants that can be loaded with these instructions include +1.0,
+0.0, log
is rounded (as specified by the RC field in the FPU control word) to external-real format.
The inexact-result exception (#P) is not generated as a result of the rounding.
Operation
TOP  TOP  1;
ST(0)  CONSTANT;
FPU Flags Affected
C1
C0, C2, C3
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1.
Floating-point Exceptions
#IS
Protected Mode Exceptions
#NM
Real Address Mode Exceptions
#NM
Volume 4: Base IA-32 Instruction Reference
Instruction
FLD1
FLDL2T
FLDL2E
FLDPI
FLDLG2
FLDLN2
FLDZ
10, log e, , log 2, and log
2 2 10
Set to 1 if stack overflow occurred; otherwise, cleared to 0.
Undefined.
Stack overflow occurred.
EM or TS in CR0 is set.
EM or TS in CR0 is set.
Description
Push +1.0 onto the FPU register stack.
Push log 10 onto the FPU register stack.
2
Push log e onto the FPU register stack.
2
Push  onto the FPU register stack.
Push log 2 onto the FPU register stack.
10
Push log 2 onto the FPU register stack.
e
Push +0.0 onto the FPU register stack.
2. For each constant, an internal 66-bit constant
e
4:139