Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1516

INS/INSB/INSW/INSD—Input from Port to String
Opcode
6C
6D
6D
6C
6D
6D
Description
Copies the data from the I/O port specified with the second operand (source operand)
to the destination operand (first operand). The source operand must be the DX register,
allowing I/O port addresses from 0 to 65,535 to be accessed. When accessing an 8-bit
I/O port, the opcode determines the port size; when accessing a 16- and 32-bit I/O
port, the operand-size attribute determines the port size.
The destination operand is a memory location at the address ES:EDI. (When the
operand-size attribute is 16, the DI register is used as the destination-index register.)
The ES segment cannot be overridden with a segment override prefix.
The INSB, INSW, and INSD mnemonics are synonyms of the byte, word, and
doubleword versions of the INS instructions. (For the INS instruction, "ES:EDI" must be
explicitly specified in the instruction.)
After the byte, word, or doubleword is transfer from the I/O port to the memory
location, the EDI register is incremented or decremented automatically according to the
setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the EDI register is
incremented; if the DF flag is 1, the EDI register is decremented.) The EDI register is
incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4
for doubleword operations.
The INS, INSB, INSW, and INSD instructions can be preceded by the REP prefix for
block input of ECX bytes, words, or doublewords.
This instruction is only useful for accessing I/O ports located in the processor's I/O
address space.
I/O transactions are performed after all prior data memory operations. No
subsequent data memory operations can pass an I/O transaction.
In the Itanium System Environment, I/O port references are mapped into the
64-bit virtual address pointed to by the IOBase register, with four ports per
4K-byte virtual page. Operating systems can utilize the TLBs in the Itanium
architecture to grant or deny permission to any four I/O ports. The I/O port
space can be mapped into any arbitrary 64-bit physical memory location by
operating system code. If CFLG.io is 1 and CPL>IOPL, the TSS is consulted for
I/O permission. If CFLG.io is 0 or CPL<=IOPL, permission is granted
regardless of the state of the TSS I/O permission bitmap (the bitmap is not
referenced).
4:214
Instruction Description
INS ES:(E)DI, DX Input byte from port DX into ES:(E)DI
INS ES:DI, DX Input word from port DX into ES:DI
INS ES:EDI, DX Input doubleword from port DX into ES:EDI
INSB Input byte from port DX into ES:(E)DI
INSW Input word from port DX into ES:DI
INSD Input doubleword from port DX into ES:EDI
Volume 4: Base IA-32 Instruction Reference