Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1697

XLAT/XLATB—Table Look-up Translation
Opcode
D7
D7
Description
Locates a byte entry in a table in memory, using the contents of the AL register as a
table index, then copies the contents of the table entry back into the AL register. The
index in the AL register is treated as unsigned integer. The XLAT and XLATB instructions
get the base address of the table in memory from the DS:EBX registers (or the DS:BX
registers when the address-size attribute of 16 bits.) The XLAT instruction allows a
different segment register to be specified with a segment override. When assembled,
the XLAT and XLATB instructions produce the same machine code.
Operation
IF AddressSize = 16
THEN
AL  (DS:BX + ZeroExtend(AL))
ELSE (* AddressSize = 32 *)
AL  (DS:EBX + ZeroExtend(AL));
FI;
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
Protected Mode Exceptions
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Volume 4: Base IA-32 Instruction Reference
Instruction Description
XLAT m8 Set AL to memory byte DS:[(E)BX + unsigned AL]
XLATB Set AL to memory byte DS:[(E)BX + unsigned AL]
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
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