Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1817

FXSAVE: Store FP and Intel
(Continued)
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #NM if CR0.EM = 1; #NM if TS bit in CR0 is set.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #AC for unaligned memory reference if the
current privilege level is 3; #PF (fault-code) for a page fault.
Additional Itanium System Environment Exceptions
Itanium Reg Faults
Itanium Mem Faults VHPT Data Fault, Data TLB Fault, Alternate Data TLB Fault, Data
State saved with FXSAVE and restored with FRSTOR (and vice versa) will result in
Notes:
incorrect restoration of state in the processor. The address size prefix will have the
usual effect on address calculation but will have no effect on the format of the FXSAVE
image.
If there is a pending unmasked FP exception at the time FXSAVE is executed, the
sequence of FXSAVE-FWAIT-FXRSTOR will result in incorrect state in the processor. The
FWAIT instruction causes the processor to check and handle pending unmasked FP
exceptions.
FSAVE), the exception is handled but that fact is not reflected in the saved image.
When the image is reloaded using FXRSTOR, the exception bits in FSW will be
incorrectly reloaded.
The use of Repeat (F2H, F3H) and Operand Size (66H) prefixes with FXSAVE is
reserved. Different processor implementations may handle this prefix differently. Use of
these prefixes with FXSAVE risks incompatibility with future processors.
Volume 4: IA-32 SSE Instruction Reference
®
MMX™ Technology State and SSE State
Disabled FP Register Fault if PSR.dfl is 1, NaT Register
Consumption Fault
Page Not Present Fault, Data NaT Page Consumption Abort, Data
Key Miss Fault, Data Key Permission Fault, Data Access Rights
Fault, Data Access Bit Fault, Data Dirty Bit Fault
Since the processor does not clear the FP state with FXSAVE (unlike
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