Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1151

st
For the sixteen_byte_form, Illegal Operation fault is raised on processor models that do
not support the instruction. CPUID register 4 indicates the presence of the feature on
the processor model. See
page 1:34
Table 2-51. Store Hints
Operation: if (PR[qp]) {
size = spill_form ? 8 : (sixteen_byte_form ? 16 : sz);
itype = WRITE;
if (size == 16) itype |= UNCACHE_OPT;
otype = (sttype == 'rel') ? RELEASE : UNORDERED;
if (sixteen_byte_form && !instruction_implemented(ST16))
illegal_operation_fault();
if (imm_base_update_form)
check_target_register(r
if (GR[r
register_nat_consumption_fault(WRITE);
paddr = tlb_translate(GR[r
if (spill_form && GR[r
natd_gr_write(GR[r
}
else {
if (sixteen_byte_form)
else
}
if (spill_form) {
bit_pos = GR[r
AR[UNAT]{bit_pos} = GR[r
}
alat_inval_multiple_entries(paddr, size);
if (imm_base_update_form) {
GR[r
GR[r
mem_implicit_prefetch(GR[r
}
}
Illegal Operation fault
Interruptions:
Register NaT Consumption fault
Unimplemented Data Address fault
Data Nested TLB fault
Alternate Data TLB fault
VHPT Data fault
3:252
Section 3.1.11, "Processor Identification Registers" on
for details.
sthint Completer
none
nta
3
].nat || ((sixteen_byte_form || normal_form) && GR[r
3
3
&tmp_unused);
].nat) {
2
], paddr, size, UM.be, mattr, otype, sthint);
2
mem_write16(GR[r ], AR[CSD], paddr, UM.be, mattr, otype, sthint);
2
mem_write(GR[r ], paddr, size, UM.be, mattr, otype, sthint);
2
]{8:3};
3
] = GR[r ] + sign_ext(imm
3 3
].nat = 0;
3
Temporal locality, level 1
Non-temporal locality, all levels
);
], size, itype, PSR.cpl, &mattr,
].nat;
2
, 9);
9
], sthint, WRITE);
3
Data Key Miss fault
Data Key Permission fault
Data Access Rights fault
Data Dirty Bit fault
Data Access Bit fault
Data Debug fault
Interpretation
].nat))
2
Volume 3: Instruction Reference