Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1776

The SFENCE (Store Fence) instruction guarantees that every store instruction that
precedes the store fence instruction in program order is globally visible before any store
instruction which follows the fence. The SFENCE instruction provides an efficient way of
ensuring ordering between routines that produce weakly-ordered results and routines
that consume this data.
4.7 IEEE Compliance
SSE floating-point computation is IEEE-754 compliant except when the control word is
set to flush to zero mode. IEEE-754 compliance includes support for single-precision
signed infinities, QNaNs, SNaNs, integer indefinite, signed zeros, denormals, masked
and unmasked exceptions. single-precision floating-point values are represented
identically both internally and in memory, and are of the following form:
Sign
31
This is a change from x87 floating-point which internally represents all numbers in
80-bit extended format. This change implies that x87-FP libraries re-written to use SSE
instructions may not produce results that are identical to the those of the x87-FP
implementation.Real Numbers and Floating-point Formats.
This section describes how real numbers are represented in floating-point format in the
processor. It also introduces terms such as normalized numbers, denormalized
numbers, biased exponents, signed zeros, and NaNs. Readers who are already familiar
with floating-point processing techniques and the IEEE standards may wish to skip this
section.
4.7.1 Real Number System
As shown in
numbers from minus infinity () to plus infinity (+).
4:474
Exponent Significand
30...23 22...0
Figure 4-8, the real-number system comprises the continuum of real
Volume 4: IA-32 SSE Instruction Reference