Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1514

INC—Increment by 1
Opcode
FE /0
FF /0
FF /0
40+ rw
40+ rd
Description
Adds 1 to the operand, while preserving the state of the CF flag. The source operand
can be a register or a memory location. This instruction allows a loop counter to be
updated without disturbing the CF flag. (Use a ADD instruction with an immediate
operand of 1 to perform a increment operation that does updates the CF flag.)
Operation
DEST  DEST - 1;
Flags Affected
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the
result.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
Protected Mode Exceptions
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Real Address Mode Exceptions
#GP
#SS
4:212
Instruction Description
INC r/m8 Increment r/m byte by 1
INC r/m16 Increment r/m word by 1
INC r/m32 Increment r/m doubleword by 1
INC r16 Increment word register by 1
INC r32 Increment doubleword register by 1
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
If the operand is located in a nonwritable segment.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it
contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
Volume 4: Base IA-32 Instruction Reference