Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1130

ptc.g, ptc.ga — Purge Global Translation Cache
( ) ptc.g
Format: qp
( ) ptc.ga
qp
The instruction and data translation cache for each processor in the local TLB coherence
Description:
domain are searched for all entries whose virtual address and page size partially or
completely overlap the specified purge virtual address and purge address range. These
entries are removed.
The purge virtual address is specified by GR
identifier is selected by GR
purge as 1<<GR[
for details on supported page sizes for TLB purges.
Based on the processor model, the translation cache may be also purged of more
translations than specified by the purge parameters up to and including removal of all
entries within the translation cache.
ptc.g has release semantics and is guaranteed to be made visible after all previous
data memory accesses are made visible. Serialization is still required to observe the
side-effects of a translation being removed. If it is desired that the ptc.g become
visible before any subsequent data memory accesses are made visible, a memory fence
instruction (mf) should be executed immediately following the ptc.g.
ptc.g must be the last instruction in an instruction group; otherwise, its behavior
(including its ordering semantics) is undefined.
The behavior of the ptc.ga instruction is similar to ptc.g. In addition to the behavior
specified for ptc.g the ptc.ga instruction encodes an extra bit of information in the
broadcast transaction. This information specifies the purge is due to a page remapping
as opposed to a protection change or page tear down. The remote processors within the
coherence domain will then take what ever additional action is necessary to make their
ALAT consistent. Matching entries in the local ALAT are optionally invalidated; software
must perform a local ALAT invalidation via the invala instruction on the processor
issuing the ptc.ga to ensure the local ALAT is coherent.
This instruction can only be executed at the most privileged level, and when PSR.vm is
0.
Unless specifically supported by the processors and platform, only one global purge
transaction may be issued at a time by all processors, the operation is undefined
otherwise. Software is responsible for enforcing this restriction. Implementations may
optionally support multiple concurrent global purge transactions. The firmware returns
if implementations support this optional behavior. It also returns the maximum number
of simultaneous outstanding purges allowed.
Propagation of ptc.g between multiple local TLB coherence domains is platform
dependent, and must be handled by software. It is expected that the local TLB
coherence domain covers at least the processors on the same local bus.
Volume 3: Instruction Reference
,
r r
3 2
,
r r
3 2
bits {63:61}. GR
r
3
]{7:2} bytes in size. See
r
2
global_alat_form
bits{60:0} and the purge region
r
3
specifies the address range of the
r
2
Section 4.1.1.7, "Page Sizes" on page 2:57
ptc.g, ptc.ga
global_form M45
M45
3:231