Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1814
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FXSAVE: Store FP and Intel
Opcode
0F,AE,/0
Operation:
m512byte = FP and MMX technology state and SSE state;
The FXSAVE instruction writes the current FP and MMX technology state and SSE state
Description:
(environment and registers) to the specified destination defined by m512byte. It does
this without checking for pending unmasked floating-point exceptions, similar to the
operation of FNSAVE. Unlike the FSAVE/FNSAVE instructions, the processor retains the
contents of the FP and MMX technology state and SSE state in the processor after the
state has been saved. This instruction has been optimized to maximize floating-point
save performance. The save data structure is as follows (little-endian byte order as
arranged in memory, with byte offset into row described by right column):
15
14
Rsrvd
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
XMM0
XMM1
XMM2
XMM3
XMM4
XMM5
XMM6
XMM7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
4:512
®
MMX™ Technology State and SSE State
Instruction
Description
FXSAVE
Store FP and Intel MMX technology state and SSE state to m512byte.
m512byte
13
12
11
10
9
CS
IP
MXCSR
ST0/MM0
ST1/MM1
ST2/MM2
ST3/MM3
ST4/MM4
ST5/MM5
ST6/MM6
ST7/MM7
8
7
6
5
4
FOP
FTW
Rsrvd
DS
Volume 4: IA-32 SSE Instruction Reference
3
2
1
0
FSW
FCW
DP
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
256
272
288
304
320
336
352
368
384
400
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