ST STM32G4 Series Reference Manual page 1874

Advanced arm-based 32-bit mcus

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Inter-integrated circuit (I2C) interface

Bit 11 ADD10: 10-bit addressing mode (master mode)

Note: Changing this bit when the START bit is set is not allowed.

Bit 10 RD_WRN: Transfer direction (master mode)

Note: Changing this bit when the START bit is set is not allowed.

Bits 9:0 SADD[9:0]: Slave address (master mode)

Note: Changing these bits when the START bit is set is not allowed.

0: The master operates in 7-bit addressing mode,

1: The master operates in 10-bit addressing mode

0: Master requests a write transfer.

1: Master requests a read transfer.

In 7-bit addressing mode (ADD10 = 0):

SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9],

SADD[8] and SADD[0] are don't care.

In 10-bit addressing mode (ADD10 = 1):

SADD[9:0] should be written with the 10-bit slave address to be sent.

RM0440 Rev 1

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