ST STM32G4 Series Reference Manual page 1796

Serial audio interface (SAI)
Bit 4 TRIS: Tristate management on data line.
This bit is set and cleared by software. It is meaningful only if the audio block is configured as a
transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be
configured when SAI is disabled.
Refer to
0: SD output line is still driven by the SAI when a slot is inactive.
1: SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one
is inactive.
Bit 3 FFLUSH: FIFO flush.
This bit is set by software. It is always read as 0. This bit should be configured when the SAI is
disabled.
0: No FIFO flush.
1: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read
and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or
received data lost). Before flushing, SAI DMA stream/interruption must be disabled
Bits 2:0 FTH[2:0]: FIFO threshold.
This bit is set and cleared by software.
000: FIFO empty
001: ¼ FIFO
010: ½ FIFO
011: ¾ FIFO
100: FIFO full
101: Reserved
110: Reserved
111: Reserved
39.5.5 Frame configuration register (SAI_AFRCR)
Address offset: 0x00C
Reset value: 0x0000 0007
Note: This register has no meaning in AC'97 and SPDIF audio protocol
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res.
rw rw rw
1796/2083
Section : Output data line management on an inactive slot
27 26 25
Res. Res. Res. Res.
11 10 9
FSALL[6:0]
rw rw rw
24 23 22
Res. Res.
8 7 6
rw rw rw
RM0440 Rev 1
for more details.
21 20 19 18
Res. Res. Res. FSOFF FSPOL FSDEF
rw
5 4 3
FRL[7:0]
rw rw rw rw
RM0440
17 16
rw r
2 1 0
rw rw