ST STM32G4 Series Reference Manual page 1898

System window watchdog (WWDG)
The formula to calculate the timeout value is given by:
where:
t
WWDG
t
PCLK
4096: value corresponding to internal divider
As an example, lets assume APB frequency is equal to 48 MHz, WDGTB[2:0] is set to 3 and
T[5:0] is set to 63:
Refer to the datasheet for the minimum and maximum values of the t
42.3.6 Debug mode
When the device enters debug mode (processor halted), the WWDG counter either
continues to work normally or stops, depending on the configuration bit in DBG module. For
more details refer to
I2C.
42.4 WWDG registers
Refer to
The peripheral registers can be accessed by halfwords (16-bit) or words (32-bit).
42.4.1 Control register (WWDG_CR)
Address offset: 0x000
Reset value: 0x0000 007F
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
1898/2083
t = t
WWDG PCLK
: WWDG timeout
: APB clock period measured in ms
t = (
WWDG
Section 1.16.2: Debug support for timers, RTC, watchdog, bxCAN and
Section 1.2 on page 71
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
WDGTB[2:0]
× 4096 × 2
1 ⁄ 48000 ) × 4096 ×
for a list of abbreviations used in register descriptions.
24 23 22
Res. Res. Res.
8 7 6
Res. WDGA
rs rw
RM0440 Rev 1
× ( T 5:0 [ ] 1 )
+
3
2 × ( 63 1 ) = 43.69ms
+
WWDG
21 20 19
Res. Res. Res.
5 4 3
T[6:0]
rw rw rw
RM0440
( ms )
.
18 17 16
Res. Res. Res.
2 1 0
rw rw rw